An arithmetic processing device includes: a pipeline circuit including an instruction fetch circuit, an instruction decoder that performs a first branch misprediction determination for a branch instruction, and issues the instructions in-order, a branch instruction processing circuit which performs a second branch misprediction determination for the branch instruction; and a commit processing circuit that executes a commit processing of the processed instructions in-order. When a branch misprediction is established in the first branch misprediction determination, the instruction decoder inhibits issuing of the instructions to the branch prediction destination from the instruction decoder, and when the first branch instruction for which the branch misprediction is established is inputted, the branch instruction processing circuit clears the pipeline state in the instruction decoder, allows the instruction fetch circuit to start fetching instructions to a correct branch destination, and releases the inhibit of issuing of the instructions from the instruction decoder.