Invention Grant
- Patent Title: Multilayer ceramic capacitor with reduced thickness
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Application No.: US16041859Application Date: 2018-07-23
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Publication No.: US10930438B2Publication Date: 2021-02-23
- Inventor: Satoshi Muramatsu , Yuki Koyama
- Applicant: Murata Manufacturing Co., Ltd.
- Applicant Address: JP Nagaokakyo
- Assignee: Murata Manufacturing Co., Ltd.
- Current Assignee: Murata Manufacturing Co., Ltd.
- Current Assignee Address: JP Nagaokakyo
- Agency: Keating & Bennett, LLP
- Priority: JPJP2017-143077 20170724,JPJP2018-087673 20180427
- Main IPC: H01G4/30
- IPC: H01G4/30 ; H01G4/232 ; H01G4/12 ; H01G4/012

Abstract:
A multilayer ceramic capacitor includes a laminate including dielectric layers and internal electrodes that are laminated, and external electrodes disposed on side surfaces of the laminate to be connected to corresponding internal electrodes. A dimension L of the multilayer ceramic capacitor in its lengthwise direction and a dimension W in its width direction satisfy: about 0.85≤W/L≤about 1, and L≤about 750 μm, and a dimension T in its lamination direction satisfies: about 70 μm≤T≤about 110 μm. The laminate has a dimension t in the lamination direction, and a region in which the internal electrodes are laminated has a dimension t′ in the lamination direction, and a ratio of the dimensions satisfies: t′/t≥about 0.55.
Public/Granted literature
- US20190027312A1 MULTILAYER CERAMIC CAPACITOR Public/Granted day:2019-01-24
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