- Patent Title: Forming self-aligned vias and air-gaps in semiconductor fabrication
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Application No.: US16257221Application Date: 2019-01-25
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Publication No.: US10930553B2Publication Date: 2021-02-23
- Inventor: Lawrence A. Clevenger , Carl J. Radens , John H. Zhang
- Applicant: TESSERA, INC.
- Applicant Address: US CA San Jose
- Assignee: TESSERA, INC.
- Current Assignee: TESSERA, INC.
- Current Assignee Address: US CA San Jose
- Agency: Lee & Hayes, P.C.
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/522 ; H01L23/528 ; H01L21/8234 ; H01L21/311
Abstract:
A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.
Public/Granted literature
- US20190172748A1 FORMING SELF-ALIGNED VIAS AND AIR-GAPS IN SEMICONDUCTOR FABRICATION Public/Granted day:2019-06-06
Information query
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