Invention Grant
- Patent Title: Buffer design for package integration
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Application No.: US16120752Application Date: 2018-09-04
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Publication No.: US10930633B2Publication Date: 2021-02-23
- Inventor: Jie Chen , Hsien-Wei Chen , Ming-Fa Chen , Chen-Hua Yu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L25/00 ; H01L25/065 ; H01L25/10 ; H01L25/18 ; H01L21/48 ; H01L21/56

Abstract:
A method of forming a package includes bonding a device die to an interposer wafer, with the interposer wafer including metal lines and vias, forming a dielectric region to encircle the device die, and forming a through-via to penetrate through the dielectric region. The through-via is electrically connected to the device die through the metal lines and the vias in the interposer wafer. The method further includes forming a polymer layer over the dielectric region, and forming an electrical connector. The electrical connector is electrically coupled to the through-via through a conductive feature in the polymer layer. The interposer wafer is sawed to separate the package from other packages.
Public/Granted literature
- US20200006309A1 Buffer Design for Package Integration Public/Granted day:2020-01-02
Information query
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