Invention Grant
- Patent Title: Circuit board
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Application No.: US16649913Application Date: 2018-09-18
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Publication No.: US10932362B2Publication Date: 2021-02-23
- Inventor: Jong Sik Lee , Jin A Gu , Soo Jung Yoon , Gyung Seok Lee , Hyun Gu Im
- Applicant: LG INNOTEK CO., LTD.
- Applicant Address: KR Seoul
- Assignee: LG INNOTEK CO., LTD.
- Current Assignee: LG INNOTEK CO., LTD.
- Current Assignee Address: KR Seoul
- Agency: Saliwanchik, Lloyd & Eisenschenk
- Priority: KR10-2017-0121885 20170921
- International Application: PCT/KR2018/010985 WO 20180918
- International Announcement: WO2019/059612 WO 20190328
- Main IPC: H05K1/03
- IPC: H05K1/03 ; H05K1/09 ; C08K3/38 ; C08K9/06 ; C09C1/00 ; C09C3/12 ; H01L33/64 ; H05K1/02 ; H05K3/46

Abstract:
A circuit board according to an embodiment of the present invention comprises: a first metal layer; an insulating layer disposed on the first metal layer and comprising boron nitride agglomerate particles coated with a resin; and a second metal layer disposed on the insulating layer, wherein: one of both surfaces of the first metal layer, on which the insulating layer is disposed, is in at least partial contact with one surface of the insulating layer; one of both surfaces of the second metal layer, on which the insulating layer is disposed, is in at least partial contact with the other surface of the insulating layer; a plurality of grooves are formed on a surface which is one of both surfaces of at least one of the first metal layer and the second metal layer and which has the insulating layer disposed thereon; at least some of the particles are arranged in at least some of the plurality of grooves; the width (W) of at least one of the plurality of grooves is 1 to 1.8 times D50 of the particles; and a ratio (D/W) of the depth (D) to the width (W) of at least one of the plurality of grooves is 0.2 to 0.3.
Public/Granted literature
- US20200315004A1 CIRCUIT BOARD Public/Granted day:2020-10-01
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