- Patent Title: Method of determining an overlay error, method for manufacturing a multilayer semiconductor device, atomic force microscopy device, lithographic system and semiconductor device
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Application No.: US16309749Application Date: 2017-06-16
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Publication No.: US10935568B2Publication Date: 2021-03-02
- Inventor: Maarten Hubertus van Es , Hamed Sadeghian Marnani
- Applicant: Nederlandse Organisatie voor toegepast-natuurwetenschappelijk onderzoek TNO
- Applicant Address: NL 's-Gravenhage
- Assignee: Nederlandse Organisatie voor toegepast-natuurwetenschappelijk onderzoek TNO
- Current Assignee: Nederlandse Organisatie voor toegepast-natuurwetenschappelijk onderzoek TNO
- Current Assignee Address: NL 's-Gravenhage
- Agency: Leydig, Voit & Mayer, Ltd.
- Priority: EP16175008 20160617
- International Application: PCT/NL2017/050398 WO 20170616
- International Announcement: WO2017/217850 WO 20171221
- Main IPC: G01Q60/32
- IPC: G01Q60/32 ; G01N21/17 ; G01N29/06 ; G01N29/275 ; G01N29/34 ; G01N29/42 ; G03F7/20 ; G03F9/00 ; G01N29/22

Abstract:
Method of determining an overlay error between device layers of a multilayer semiconductor device using an atomic force microscopy system, wherein the semiconductor device comprises a stack of device layers comprising a first patterned layer and a second patterned layer, and wherein the atomic force microscopy system comprises a probe tip, wherein the method comprises: moving the probe tip and the semiconductor device relative to each other for scanning of the surface; and monitoring motion of the probe tip with tip position detector during said scanning for obtaining an output signal; during said scanning, applying a first acoustic input signal to at least one of the probe or the semiconductor device; analyzing the output signal for mapping at least subsurface nanostructures below the surface of the semiconductor device; and determining the overlay error between the first patterned layer and the second patterned layer based on the analysis.
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