A semiconductor apparatus includes a clock control circuit that at least one of generates a plurality of latch control clocks, which are periodically transitioned, in response to a power saving mode signal and a clock, and individually locks each of the plurality of latch control clocks to one of multiple levels regardless of the clock. The semiconductor apparatus also includes a latch circuit that stores an input signal in response to the plurality of latch control clocks and outputs the stored signal as an output signal.