Invention Grant
- Patent Title: Error correction scheme in flash memory
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Application No.: US16455857Application Date: 2019-06-28
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Publication No.: US10936415B2Publication Date: 2021-03-02
- Inventor: Chris Yip , Piyush Sagdeo , Gautam Dusija , Vidhu Gupta
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Dickinson Wright PLLC
- Agent Steven Hurles
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G06F11/16 ; G06F12/02 ; G06F13/16

Abstract:
An error correction scheme in flash memory. Methods include extending a lifetime of a memory block, including: receiving an indication that an error occurred during a write operation at a first location in a memory block, the first location associated with a faulty page of the memory block; and performing a modified exclusive OR (XOR) scheme on the memory block by: performing a de-XOR operation that generates recovery data of the faulty page; storing the recovery data in a location different from the faulty page of memory; marking the faulty page for exclusion in future de-XOR operations; and performing a parity calculation that generates an updated parity value that includes all pages of the memory block that have been programmed except for the faulty page.
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