In one or more embodiments, one or more systems, methods, and/or processes may determine a Peripheral Component Interconnect Express (PCIe) endpoint, associated with a PCIe destination endpoint identification, includes a field programmable gate array (FPGA); may access a partial configuration for the FPGA; may construct multiple packets that include the PCIe destination endpoint identification and respective portions of the partial configuration for the FPGA; and may provide the multiple packets to the PCIe endpoint. In one or more embodiments, the one or more systems, methods, and/or processes may further map at least a portion of the FPGA to a virtual machine. In one or more embodiments, the one or more systems, methods, and/or processes may further combine the portions of the partial configuration for the FPGA to reconstruct the partial configuration for the FPGA; and may further program the FPGA with the partial configuration for the FPGA.