Invention Grant
- Patent Title: Inter-cell leakage-reducing method of generating layout diagram and system for same
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Application No.: US16547065Application Date: 2019-08-21
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Publication No.: US10936785B2Publication Date: 2021-03-02
- Inventor: Hiranmay Biswas , Chung-Hsing Wang , Kuo-Nan Yang , Jia Han Lin
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Hauptman Ham, LLP
- Main IPC: G06F30/398
- IPC: G06F30/398 ; G06F119/18 ; G03F7/20 ; H01L27/092 ; H01L27/02 ; G06F30/392

Abstract:
A method (of manufacturing a semiconductor device) includes, for a layout diagram stored on a non-transitory computer-readable medium, generating the layout diagram including: populating a row which extends in a first direction with a group of cells, each cell representing a circuit, and first and second side boundaries of each cell being substantially parallel and extending in a second direction which is substantially perpendicular to the first direction; locating, relative to the first direction, cells so that neighboring ones of the cells are substantially abutting; and reducing an aggregate leakage tendency of the group by performing at least one of the following, (A) changing an orientation of at least one of the cells, or (B) changing locations correspondingly of at least two of the cells.
Public/Granted literature
- US20200074042A1 INTER-CELL LEAKAGE-REDUCING METHOD OF GENERATING LAYOUT DIAGRAM AND SYSTEM FOR SAME Public/Granted day:2020-03-05
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