Fuse latch circuits and related systems, methods, and apparatuses are disclosed. An apparatus includes a half interlock latch circuit including a first half and a second half. The first half of the half interlock latch circuit is configured to operate in a high impedance state responsive to operation of the second half of the half interlock latch circuit in a driven state. The second half of the half interlock latch circuit is configured to operate in a high impedance state responsive to operation of the first half of the half interlock latch circuit in a driven state.