Invention Grant
- Patent Title: Multiple patterning scheme integration with planarized cut patterning
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Application No.: US16669835Application Date: 2019-10-31
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Publication No.: US10937653B2Publication Date: 2021-03-02
- Inventor: Hsueh-Chung Chen , Yongan Xu , Lawrence A. Clevenger , Yann Mignot , Cornelius Brown Peethala
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent James Nock
- Main IPC: H01L21/033
- IPC: H01L21/033 ; H01L21/027 ; H01L21/02 ; H01L21/3105 ; G03F7/00 ; G03F7/16 ; G03F7/20 ; G03F7/09
Abstract:
A method for fabricating a semiconductor device integrating a multiple patterning scheme includes forming a memorization layer over a plurality of mandrels and a plurality of non-mandrels, and applying an exposure scheme to the memorization layer to form at least one mandrel cut pattern and at least one non-mandrel cut pattern.
Public/Granted literature
- US20200066525A1 MULTIPLE PATTERNING SCHEME INTEGRATION WITH PLANARIZED CUT PATTERNING Public/Granted day:2020-02-27
Information query
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