Invention Grant
- Patent Title: Method for reducing via RC delay
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Application No.: US15624879Application Date: 2017-06-16
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Publication No.: US10937692B2Publication Date: 2021-03-02
- Inventor: Jiquan Liu
- Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION , SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
- Applicant Address: CN Beijing; CN Shanghai
- Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION,SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
- Current Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION,SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
- Current Assignee Address: CN Beijing; CN Shanghai
- Agency: Anova Law Group, PLLC
- Priority: CN201610532198.7 20160707
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/285 ; H01L23/522 ; H01L23/532

Abstract:
A method for manufacturing an interconnect structure includes providing a substrate structure including a substrate, a first metal layer on the substrate, a dielectric layer on the substrate and covering the first metal layer, and an opening extending to the first metal layer; forming a first barrier layer on a bottom and sidewalls of the opening with a first substrate bias; forming a second barrier layer on the first barrier layer with a second substrate bias, the second substrate bias being greater than the first substrate bias, the first and second barrier layers forming collectively a barrier layer; removing a portion of the barrier layer on the bottom and on the sidewalls of the opening by bombarding the barrier layer with a plasma with a vertical substrate bias; and forming a second metal layer filling the opening.
Public/Granted literature
- US20180012797A1 METHOD FOR REDUCING VIA RC DELAY Public/Granted day:2018-01-11
Information query
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