Invention Grant
- Patent Title: Method of forming a fin under a gate structure
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Application No.: US16406208Application Date: 2019-05-08
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Publication No.: US10937699B2Publication Date: 2021-03-02
- Inventor: Jhon Jhy Liaw
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L29/78 ; H01L29/66 ; H01L21/762 ; H01L21/8238 ; H01L21/84 ; H01L27/088 ; H01L27/092 ; H01L27/12 ; H01L29/10

Abstract:
A method for forming a semiconductor device includes forming a fin structure on a substrate, forming a shallow trench isolation region adjacent the fin structure so that an upper portion of the fin structure is exposed, forming a dummy gate over the exposed fin structure, forming an interlayer dielectric layer around the dummy gate, removing the dummy gate to expose the fin structure, and after removing the dummy gate, introducing a strain into a crystalline structure of the exposed fin structure.
Public/Granted literature
- US20190267290A1 METHOD OF FORMING A FIN UNDER A GATE STRUCTURE Public/Granted day:2019-08-29
Information query
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