Invention Grant
- Patent Title: Wiring board and display device including metal line with redundant structure and reduced wiring resistance
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Application No.: US16383873Application Date: 2019-04-15
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Publication No.: US10937814B2Publication Date: 2021-03-02
- Inventor: Masahiro Yoshida
- Applicant: Sharp Kabushiki Kaisha
- Applicant Address: JP Sakai
- Assignee: Sharp Kabushiki Kaisha
- Current Assignee: Sharp Kabushiki Kaisha
- Current Assignee Address: JP Sakai
- Agency: Keating & Bennett, LLP
- Priority: JPJP2018-078428 20180416
- Main IPC: H01L27/12
- IPC: H01L27/12 ; G02F1/1368 ; G02F1/1362 ; G06F3/044 ; G02F1/1333 ; G02F1/1339 ; G02F1/1343

Abstract:
An array substrate includes gate lines made of a first metal film, source lines made of a second metal film disposed such that a gate insulating film is interposed between the second metal film and the first metal film, the source lines extending to intersect the gate lines, auxiliary lines made of the first metal film, the auxiliary lines being arranged such that a pair of auxiliary lines sandwich the gate line therebetween and extending in parallel with the source lines to at least partly overlap the source lines, respectively, and bridge lines made of a third metal film disposed such that a first inter-layer film located opposite to the gate insulating film is interposed between the third metal film and the second metal film, the bridge lines being arranged to lie astride the gate lines, respectively, to electrically connect the source lines to pairs of the auxiliary lines.
Public/Granted literature
- US20190319052A1 WIRING BOARD AND DISPLAY DEVICE Public/Granted day:2019-10-17
Information query
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