An array substrate has a display area and a non-display area disposed at a periphery of the display area. The array substrate includes: a base substrate; at least one gate driver on array (GOA) circuit disposed on the base substrate and disposed in the non-display area; a planarization layer disposed on a side of the at least one GOA circuit facing away from the base substrate; and at least one electrostatic protection portion disposed on a surface of the planarization layer facing away from the base substrate and disposed in the non-display area. An orthographic projection of each GOA circuit on the base substrate is located within an outer boundary of an orthographic projection of a corresponding electrostatic protection portion on the base substrate.