Invention Grant
- Patent Title: Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack
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Application No.: US16399845Application Date: 2019-04-30
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Publication No.: US10937861B2Publication Date: 2021-03-02
- Inventor: Injo Ok , Balasubramanian Pranatharthiharan , Soon-Cheon Seo , Charan V. V. S. Surisetty
- Applicant: TESSERA, INC.
- Applicant Address: US CA San Jose
- Assignee: TESSERA, INC.
- Current Assignee: TESSERA, INC.
- Current Assignee Address: US CA San Jose
- Agency: Lee & Hayes, P.C.
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/764 ; H01L21/762 ; H01L21/3105 ; H01L21/3213 ; H01L21/3065 ; H01L29/49 ; H01L23/485 ; H01L21/768 ; H01L21/8234 ; H01L23/532 ; H01L23/535 ; H01L27/088 ; H01L29/161

Abstract:
A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.
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