Invention Grant
- Patent Title: III-V transistor device with self-aligned doped bottom barrier
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Application No.: US15884503Application Date: 2018-01-31
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Publication No.: US10937871B2Publication Date: 2021-03-02
- Inventor: Cheng-Wei Cheng , Pranita Kerber , Amlan Majumdar , Yanning Sun
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent L. Jeffrey Kelly
- Main IPC: H01L29/205
- IPC: H01L29/205 ; H01L29/66 ; H01L21/306 ; H01L21/762 ; H01L29/51 ; H01L29/45 ; H01L29/417 ; H01L21/265 ; H01L29/207 ; H01L29/06

Abstract:
A semiconductor device comprises a first layer of a substrate arranged on a second layer of the substrate the second layer of the substrate including a doped III-V semiconductor material barrier layer, a gate stack arranged on a channel region of the first layer of a substrate, a spacer arranged adjacent to the gate stack on the first layer of the substrate, an undoped epitaxially grown III-V semiconductor material region arranged on the second layer of the substrate, and an epitaxially grown source/drain region arranged on the undoped epitaxially grown III-V semiconductor material region, and a portion of the first layer of the substrate.
Public/Granted literature
- US20180151674A1 III-V TRANSISTOR DEVICE WITH SELF-ALIGNED DOPED BOTTOM BARRIER Public/Granted day:2018-05-31
Information query
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