Invention Grant
- Patent Title: Semiconductor device with negative capacitance material in buried channel
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Application No.: US16297747Application Date: 2019-03-11
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Publication No.: US10937886B2Publication Date: 2021-03-02
- Inventor: Ching-Chia Huang , Tseng-Fu Lu , Wei-Ming Liao
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agency: CKC & Partners Co., LLC
- Main IPC: H01L29/51
- IPC: H01L29/51 ; H01L29/78 ; H01L29/423

Abstract:
A semiconductor device includes a substrate, at least one trench, an insulating layer, a lower metal layer, a negative capacitance material layer, and an upper metal layer. The trench has an inner surface in the substrate. The insulating layer is disposed on and lining the inner surface of the trench. The lower metal layer is disposed on the insulating layer and partially filling the trench. The negative capacitance material layer is disposed on and lining the insulating layer and the lower metal layer, in which a remained portion of the trench is defined by the negative capacitance material layer. The upper metal layer is disposed on the negative capacitance material layer and filling the remained portion of the trench.
Public/Granted literature
- US20200185507A1 SEMICONDUCTOR DEVICE WITH NEGATIVE CAPACITANCE MATERIAL IN BURIED CHANNEL Public/Granted day:2020-06-11
Information query
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