Invention Grant
- Patent Title: Method for minimizing DC capacitance for cascade multilevel converter
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Application No.: US16901170Application Date: 2020-06-15
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Publication No.: US10938320B2Publication Date: 2021-03-02
- Inventor: Xiaoqiang Guo , Lichong Wang , Hao Ding , Chaozhe Wang , Zhigang Lu , Baocheng Wang
- Applicant: SHENK ELECTRIC INC. , Yanshan University
- Applicant Address: CN Shijiazhuang; CN Qinhuangdao
- Assignee: SHENK ELECTRIC INC.,Yanshan University
- Current Assignee: SHENK ELECTRIC INC.,Yanshan University
- Current Assignee Address: CN Shijiazhuang; CN Qinhuangdao
- Agency: IPro, PLLC
- Priority: CN2019105478506 20190624
- Main IPC: H02M7/49
- IPC: H02M7/49 ; H02M7/48 ; H02M7/483 ; H02M1/00

Abstract:
A method for minimizing DC capacitance of a cascade multilevel converter is provided. On the basis of balancing of capacitor voltages, the method estimates instantaneous value of the DC side capacitor voltages in a circuit through an energy conservation law, and uses a proportional resonance controller to control a grid-connected current to realize adjustment of the grid-connected current without static difference, such that the cascade multilevel converter can operate in a small capacitance mode, the system volume is greatly reduced, the system cost is reduced, the control is easy to be implemented, and the capacitor voltage is free from overshoot and the system has a better rapidity.
Information query
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