Invention Grant
- Patent Title: Evaluation of bit error vectors for symbol error analysis
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Application No.: US16439262Application Date: 2019-06-12
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Publication No.: US10938513B2Publication Date: 2021-03-02
- Inventor: Reiner Schnizler
- Applicant: VIAVI SOLUTIONS INC.
- Applicant Address: US CA San Jose
- Assignee: VIAVI SOLUTIONS INC.
- Current Assignee: VIAVI SOLUTIONS INC.
- Current Assignee Address: US CA San Jose
- Agency: Mannava & Kang, P.C.
- Main IPC: H04L1/00
- IPC: H04L1/00 ; H04L1/20

Abstract:
The disclosure relates to evaluating bit error vectors for symbol error analysis on real-world framed signals. Forward error correction (FEC) may generate a bit error vector to correct binary lanes such as non-return-to-zero (NRZ) lanes demultiplexed from a symbol-encoding lane such as a 4-level pulse amplitude modulation (PAM-4) lane. An apparatus may apply the bit error vector to the demultiplexed NRZ lanes to identify bit errors that occurred on the NRZ lanes. The apparatus may map the bit errors on the NRZ lanes to symbol errors on the PAM-4 lane. The apparatus may generate detailed symbol error information based on the identified symbol errors. The symbol error information may then be used for link tuning, thereby mitigating the effects of high frequency physical effects and other impairments on high-speed data links.
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