Invention Grant
- Patent Title: Semiconductor storage circuit
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Application No.: US16847551Application Date: 2020-04-13
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Publication No.: US10943643B2Publication Date: 2021-03-09
- Inventor: Masataka Sato , Hideo Akiyoshi , Masanobu Hirose , Yoshinobu Yamagami
- Applicant: SOCIONEXT INC.
- Applicant Address: JP Kanagawa
- Assignee: SOCIONEXT INC.
- Current Assignee: SOCIONEXT INC.
- Current Assignee Address: JP Kanagawa
- Agency: McDermott Will & Emery LLP
- Main IPC: G11C11/408
- IPC: G11C11/408 ; G11C5/02 ; G11C11/4099

Abstract:
First and second memory cell arrays each having memory cells arranged in the X and Y directions lie side by side in the Y direction with space between them. A relay buffer is provided between first and second row decoders for buffering a control signal to be supplied to the second row decoder. An inter-array block between the first and second memory cell arrays is constituted by at least either a tap cell or a dummy memory cell. The relay buffer and the inter-array block are the same in position and size in the Y direction.
Public/Granted literature
- US20200243128A1 SEMICONDUCTOR STORAGE CIRCUIT Public/Granted day:2020-07-30
Information query
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