Invention Grant
- Patent Title: Silicon and silicon germanium nanowire formation
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Application No.: US16599307Application Date: 2019-10-11
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Publication No.: US10943833B2Publication Date: 2021-03-09
- Inventor: Kuo-Cheng Chiang , Carlos H. Diaz , Jean-Pierre Colinge
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L21/8238 ; B82Y10/00 ; B82Y40/00 ; H01L29/66 ; H01L29/786 ; H01L29/775 ; H01L29/06 ; H01L27/092 ; H01L29/16 ; H01L29/78

Abstract:
Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.
Public/Granted literature
- US20200051870A1 Silicon and Silicon Germanium Nanowire Formation Public/Granted day:2020-02-13
Information query
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