Invention Grant
- Patent Title: High-speed and low-noise dynamic comparator
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Application No.: US16620526Application Date: 2018-07-18
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Publication No.: US10944390B2Publication Date: 2021-03-09
- Inventor: Daiguo Xu , Gangyi Hu , Ruzhang Li , Jian'an Wang , Guangbing Chen , Dongbing Fu , Shiliu Xu , Tao Liu , Jie Pu , Zhihua Feng
- Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATIO
- Applicant Address: CN Chongqing
- Assignee: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATIO
- Current Assignee: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATIO
- Current Assignee Address: CN Chongqing
- Priority: CN201810239481.X 20180322
- International Application: PCT/CN2018/096084 WO 20180718
- International Announcement: WO2019/178988 WO 20190926
- Main IPC: H03K5/22
- IPC: H03K5/22 ; H03K5/24 ; H03K19/20

Abstract:
The present disclosure provides a high-speed and low-noise dynamic comparator, which includes: an input unit, including an input NMOS transistor and an input PMOS transistor; a latch unit, including a latching NMOS transistor and a latching PMOS transistor, where the latching NMOS transistor and the latching PMOS transistor are connected to form a latch structure; a pull-up unit, including a pull-up PMOS transistor connected to the input NMOS transistor; and a substrate bootstrap voltage generation circuit, generating a substrate bootstrap voltage. In the present disclosure, a substrate bootstrap technology of MOS transistors is used, thereby reducing on resistances of the MOS transistors and improving the comparator speed; threshold voltages of the input transistors of the comparator are reduced, transconductance of the input transistors is increased, thereby reducing equivalent input noise of the comparator, and as a common-mode voltage of the comparator changes, a comparison delay changes relatively little.
Information query
IPC分类: