Invention Grant
- Patent Title: Assembling and handling edge interconnect packaging system
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Application No.: US15817727Application Date: 2017-11-20
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Publication No.: US10945335B2Publication Date: 2021-03-09
- Inventor: Jason M. Kulick , Tian Lu
- Applicant: Indiana Integrated Circuits, LLC
- Applicant Address: US IN South Bend
- Assignee: Indiana Integrated Circuits, LLC
- Current Assignee: Indiana Integrated Circuits, LLC
- Current Assignee Address: US IN South Bend
- Agency: The Webb Law Firm
- Main IPC: H05K1/18
- IPC: H05K1/18 ; H05K1/11 ; H05K3/34

Abstract:
Apparatuses and methods related to the field of microchip assembly and handling, in particular to devices and methods for assembling and handling microchips manufactured with solid edge-to-edge interconnects, such as Quilt Packaging® interconnect technology. Specialized assembly tools are configured to pick up one or more microchips, place the microchips in a specified location aligned to a substrate, package, or another microchip, and facilitate electrical contact through one of a variety of approaches, including solder reflow. This specialized assembly tooling performs heating functions to reflow solder to establish electrical and mechanical interconnections between multiple microchips. Additionally, the interconnected microchips may be arranged in an arbitrarily large array.
Public/Granted literature
- US20180077801A1 Assembling and Handling Edge Interconnect Packaging System Public/Granted day:2018-03-15
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