- Patent Title: Bias circuit, image formation device and image forming apparatus
-
Application No.: US16574436Application Date: 2019-09-18
-
Publication No.: US10948854B2Publication Date: 2021-03-16
- Inventor: Hiroshi Okamura
- Applicant: Hiroshi Okamura
- Applicant Address: JP Kanagawa
- Assignee: Hiroshi Okamura
- Current Assignee: Hiroshi Okamura
- Current Assignee Address: JP Kanagawa
- Agency: IPUSA, PLLC
- Priority: JPJP2018-182880 20180927
- Main IPC: G03G15/16
- IPC: G03G15/16 ; G03G15/00 ; G05F3/18 ; G03G21/16 ; H01L29/866

Abstract:
A bias circuit includes one or more first Zener diodes electrically coupled to a member provided in a replacement unit, the one or more first Zener diodes being coupled in series. When the replacement unit is removably attached to a main unit including a power supply that has one or more second Zener diodes coupled in series, the first Zener diodes are electrically coupled to the second Zener diodes in parallel to change a bias voltage to be applied to the member, the bias voltage being supplied by the power supply. A total absolute value of breakdown voltages across the first Zener diodes is lower than a total absolute value of breakdown voltages across the second Zener diodes.
Information query