Invention Grant
- Patent Title: NAND device mixed parity management
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Application No.: US16210730Application Date: 2018-12-05
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Publication No.: US10949297B2Publication Date: 2021-03-16
- Inventor: Giuseppe Cariello
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G11C29/42 ; G11C29/52
Abstract:
Devices and techniques for NAND device mixed parity management are described herein. A first portion of data that corresponds to a first data segment and a second data segment—respectively defined with respect to a structure of a NAND device—are received. A parity value using the first portion of data and the second portion of data is computed and then stored for error correction operations.
Public/Granted literature
- US20200183779A1 NAND DEVICE MIXED PARITY MANAGEMENT Public/Granted day:2020-06-11
Information query
