System and method of reducing logic for multi-bit error correcting codes
Abstract:
A method of generating an error correction circuit for correcting an error in a codeword read from a memory includes: constructing a G matrix; transforming the G matrix into a systematic form, the transformed G matrix composed of a P matrix and a H matrix; sorting rows of the P matrix according to row weights; determining the number of rows in the P matrix to be truncated in view of a correcting strength and the number of data bits; generating a truncated P matrix by truncating the sorted rows of the P matrix that have a first row weights and keeping the sorted rows of the P matrix that have a second row weights; and forming the error correction circuit according to the truncated P matrix to correct the error of the codeword; wherein the first row weights are greater than the second row weights.
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