Invention Grant
- Patent Title: System and method of reducing logic for multi-bit error correcting codes
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Application No.: US16285677Application Date: 2019-02-26
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Publication No.: US10949298B2Publication Date: 2021-03-16
- Inventor: Shih-Lien Linus Lu
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Marquez IP Law Office, PLLC
- Agent Juan Carlos A. Marquez
- Main IPC: G06F11/10
- IPC: G06F11/10 ; H03M13/00 ; G11C29/52 ; G06F11/22

Abstract:
A method of generating an error correction circuit for correcting an error in a codeword read from a memory includes: constructing a G matrix; transforming the G matrix into a systematic form, the transformed G matrix composed of a P matrix and a H matrix; sorting rows of the P matrix according to row weights; determining the number of rows in the P matrix to be truncated in view of a correcting strength and the number of data bits; generating a truncated P matrix by truncating the sorted rows of the P matrix that have a first row weights and keeping the sorted rows of the P matrix that have a second row weights; and forming the error correction circuit according to the truncated P matrix to correct the error of the codeword; wherein the first row weights are greater than the second row weights.
Public/Granted literature
- US20200097360A1 SYSTEM AND METHOD OF REDUCING LOGIC FOR MULTI-BIT ERROR CORRECTING CODES Public/Granted day:2020-03-26
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