Invention Grant
- Patent Title: Memory device with multiple layers
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Application No.: US16109365Application Date: 2018-08-22
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Publication No.: US10950617B2Publication Date: 2021-03-16
- Inventor: Hideto Takekida
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Tokyo
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Kim & Stewart LLP
- Priority: JPJP2018-045645 20180313
- Main IPC: H01L27/11582
- IPC: H01L27/11582 ; H01L27/11524 ; H01L29/10 ; G11C16/08 ; G11C16/24 ; G11C16/04 ; H01L27/11556 ; H01L27/1157 ; H01L23/528 ; H01L21/02 ; H01L21/311 ; H01L21/28
Abstract:
A memory device includes a plurality of word lines spaced from one another in a first direction, a first insulating film provided between adjacent word lines, a plurality of select gates located above the plurality of word lines in the first direction, a first intermediate electrode provided between the plurality of word lines and the select gates, a second insulating film provided between the first intermediate electrode and the select gates, a semiconductor pillar extending through the plurality of word lines, the first insulating film, the first intermediate electrode, the second insulating film, and the select gates, and extending in the first direction, and a charge retention film located between each of the plurality of word lines and the semiconductor pillar, wherein the second insulating film has a second thickness in the first direction that is greater than a first thickness of the first insulating film in the first direction.
Public/Granted literature
- US20190287988A1 MEMORY DEVICE Public/Granted day:2019-09-19
Information query
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