Disclosed herein is a memory controller controlling data transfer between a host system and a flash memory. The memory controller is configured to operate on one of a plurality of operation states including first and second operation states. In the first operation state, a first memory area included in the flash memory is used in a first storage mode that stores information of less than n bits in one cell, and a second memory area included in the flash memory is used in a second storage mode that stores information of n bits or more in one cell. In the second operation state, the first memory area is used in the second storage mode, and the second memory area is used in the first storage mode.