Invention Grant
- Patent Title: Post completion execution in an out-of-order processor design
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Application No.: US16296621Application Date: 2019-03-08
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Publication No.: US10956168B2Publication Date: 2021-03-23
- Inventor: Avery Francois , Christian Jacobi , Gregory William Alexander
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent William Kinnaman
- Main IPC: G06F9/38
- IPC: G06F9/38

Abstract:
A computer data processing system includes an instruction pipeline having a front end and a back end, a decoding and dispatch unit to dispatch a current instruction; and a pipeline by-pass unit to invoke an out-of-order pipeline by-pass operation. The pipeline by-pass unit by-passes a section of the instruction pipeline such that the current instruction architecturally completes before initiating instruction execution. The computer data processing system further includes a post-completion execution unit that executes the current instruction after the current instruction architecturally completes.
Public/Granted literature
- US20200285482A1 POST COMPLETION EXECUTION IN AN OUT-OF-ORDER PROCESSOR DESIGN Public/Granted day:2020-09-10
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