Invention Grant
- Patent Title: Pulse width modulation output stage with dead time control
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Application No.: US16837634Application Date: 2020-04-01
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Publication No.: US10958259B2Publication Date: 2021-03-23
- Inventor: Szu-Chun Tsao , Yang-Jing Huang , Ya-Mien Hsu
- Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
- Applicant Address: TW Hsinchu
- Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
- Current Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
- Current Assignee Address: TW Hsinchu
- Agency: Marquez IP Law Office, PLLC
- Agent Juan Carlos A. Marquez
- Priority: TW108119647 20190604
- Main IPC: H03K7/08
- IPC: H03K7/08

Abstract:
A pulse width modulation output stage incorporates a half bridge output stage, a gate control circuit, a detection circuit, and a control logic. The half bridge output stage has a first transistor and a second transistor connected in series between a power supply node and a ground node. The gate control circuit outputs a pulse width modulation signal to drive the first transistor and the second transistor. The detection circuit detects whether or not a glitch occurs in one of the gate voltages of the first and second transistor so as to generate a control code. The logic circuit varies the delay time of the pulse width modulation signal based on the control code.
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