Invention Grant
- Patent Title: Dual purpose on-chip buffer memory for low latency switching
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Application No.: US16249820Application Date: 2019-01-16
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Publication No.: US10958575B2Publication Date: 2021-03-23
- Inventor: Keshav G. Kamble , Abhijit P. Kumbhare , Harshad S. Padhye , Vijoy A. Pandey
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Zilka-Kotab, P.C.
- Main IPC: H04L12/28
- IPC: H04L12/28 ; H04L12/741 ; H04L29/06 ; H04L12/54 ; H04L12/46 ; H04L12/771 ; H04L12/823 ; H04L12/805 ; H04L12/931

Abstract:
In one embodiment, an apparatus includes a buffer memory, at least one ingress port, at least one egress port, at least one processor, and logic integrated with and/or executable by the at least one processor, the logic being configured to communicate with a software-defined network (SDN) controller, store one or more look-up tables in a first portion of the buffer memory, receive a packet using an ingress port, and determine an egress port for the packet. In another embodiment, a method for switching packets in a SDN includes storing one or more look-up tables in a first portion of a buffer memory of a SDN-capable switching device, receiving a packet using an ingress port of the switching device, and determining an egress port for the packet.
Public/Granted literature
- US20190149471A1 DUAL PURPOSE ON-CHIP BUFFER MEMORY FOR LOW LATENCY SWITCHING Public/Granted day:2019-05-16
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