Hardware assisted remote transactional memory including receiving, from a first remote processor over a high-speed communications fabric, an indication of a beginning of a first memory transaction; queuing, in a first hardware memory assistant, memory instructions for the first memory transaction; receiving, from a second remote processor over the high-speed communications fabric, an indication of a beginning of a second memory transaction; queuing, in a second hardware memory assistant, memory instructions for the second memory transaction; receiving, from the first remote processor over the high-speed communications fabric, an indication of an ending of the first memory transaction; comparing memory addresses accessed in the first memory transaction to memory addresses accessed in the second memory transaction; and in response to determining that the memory addresses accessed in the first memory transaction overlap with the memory addresses accessed in the second memory transaction, aborting the first memory transaction.