[Object] An object is to suppress an occurrence of display unevenness in a pause-and-drive operation.
[Solution] A display device configured to perform pause-and-drive operation includes an nth stage circuit connected to one end of an nth gate bus line, and an nth transistor connected to the other end of the nth gate bus line. One of a first clock signal group (AGCK1 to AGCK6) is input to the nth stage circuit. One of a second clock signal group (BGCK1 to BGCK6) is input to the nth transistor. In a pause period in which all clock signals of the first clock signal group are fixed at an inactive level, one or more pulses (P3 to P6) are included in the second signal group.