Invention Grant
- Patent Title: Method for forming a fin-based semiconductor structure
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Application No.: US16537123Application Date: 2019-08-09
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Publication No.: US10964585B2Publication Date: 2021-03-30
- Inventor: Zhang Tianhao , Wu Yichao
- Applicant: Semiconductor Manufacturing International (Beijing) Corporation , Semiconductor Manufacturing International (Shanghai) Corporation
- Applicant Address: CN Beijing; CN Shanghai
- Assignee: Semiconductor Manufacturing International (Beijing) Corporation,Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee: Semiconductor Manufacturing International (Beijing) Corporation,Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee Address: CN Beijing; CN Shanghai
- Agency: Brinks Gilson & Lione
- Priority: CN201811605458.4 20181226
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L21/762 ; H01L29/66 ; H01L21/311 ; H01L29/78 ; H01L21/02 ; H01L29/06 ; H01L21/306 ; H01L21/308 ; H01L21/3065 ; H01L21/8238

Abstract:
Disclosed are a semiconductor structure and a method for forming same. One form of the forming method includes: providing a base, including a substrate and a fin protruding out of the substrate, where a fin mask layer is formed on the top of the fin, and the base includes a graphics-intensive region and a graphics-sparse region; forming an isolation material layer on the substrate exposed by the fin, to expose a top of the fin mask layer; performing first etching processing on the isolation material layer, where a residual isolation material layer covers a partial sidewall of the fin mask layer, and a top of the residual isolation material layer located on the graphics-sparse region is lower than a top of the residual isolation material layer located on the graphics-intensive region; removing the fin mask layer after the first etching processing is performed; and performing second etching processing on the residual isolation material layer using an isotropic dry etching process after the fin mask layer is removed, where the etched isolation material layer is used as an isolation layer, and the isolation layer covers a partial sidewall of the fin. Embodiments of the present disclosure help to improve the height consistency of the tops of isolation layers located on different graphics density regions, thereby improving the performance of the semiconductor structure.
Public/Granted literature
- US20200211894A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME Public/Granted day:2020-07-02
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