Invention Grant
- Patent Title: Method and apparatus of ESD protection in stacked die semiconductor device
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Application No.: US16230700Application Date: 2018-12-21
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Publication No.: US10964651B2Publication Date: 2021-03-30
- Inventor: Jen-Chou Tseng , Tzu-Heng Chang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/60
- IPC: H01L23/60 ; H01L23/00 ; H01L27/02 ; H01L25/065 ; H01L23/498 ; H01L25/00

Abstract:
An apparatus includes an interposer and a plurality of dies stacked on the interposer. The interposer includes a first conductive network of a first trigger bus. Each of the plurality of dies includes a second conductive network of a second trigger bus, and an ESD detection circuit and an ESD power clamp electrically connected between a first power line and a second power line, and electrically connected to the second conductive network of the second trigger bus. The second conductive network of the second trigger bus in each of the plurality of dies is electrically connected to the first conductive network of the first trigger bus. Upon receiving an input signal, the ESD detection circuit is configured to generate an output signal to the corresponding second conductive network of the second trigger bus to control the ESD power clamps in each of the plurality of dies.
Public/Granted literature
- US20190123001A1 Method and Apparatus of ESD Protection in Stacked Die Semiconductor Device Public/Granted day:2019-04-25
Information query
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