Invention Grant
- Patent Title: Stacked transistor packages
-
Application No.: US15907840Application Date: 2018-02-28
-
Publication No.: US10964668B2Publication Date: 2021-03-30
- Inventor: Jose Miguel Salgado Escuadra
- Applicant: PGS Geophysical AS
- Applicant Address: NO Oslo
- Assignee: PGS Geophysical AS
- Current Assignee: PGS Geophysical AS
- Current Assignee Address: NO Oslo
- Main IPC: G01V1/20
- IPC: G01V1/20 ; H01L25/065 ; H01L23/02

Abstract:
Transistor packages in space-constrained applications are disclosed. An apparatus may comprise a first transistor package and a second transistor package, wherein the first transistor package is stacked upon the second transistor package. The apparatus may further comprise a cover coupled to a printed circuit board (PCB) that is configured to cover at least a portion of the stacked first and second transistor packages. The first and second transistor package may be components in a power circuit that is configured to down-convert a received voltage from a first voltage level to a second, lower voltage level.
Public/Granted literature
- US20180247918A1 STACKED TRANSISTOR PACKAGES Public/Granted day:2018-08-30
Information query