Invention Grant
- Patent Title: Through silicon via design for stacking integrated circuits
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Application No.: US16578299Application Date: 2019-09-21
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Publication No.: US10964692B2Publication Date: 2021-03-30
- Inventor: Kong-Beng Thei , Dun-Nian Yaung , Fu-Jier Fan , Hsing-Chih Lin , Hsiao-Chin Tuan , Jen-Cheng Liu , Alexander Kalnitsky , Yi-Sheng Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L27/06 ; H01L23/48 ; H01L23/00 ; H01L23/522 ; H01L23/31 ; H01L21/48

Abstract:
A three-dimensional (3D) integrated circuit (IC) and associated forming method are provided. In some embodiments, a second IC die is bonded to a first IC die through a second bonding structure and a first bonding structure at a bonding interface. The bonding encloses a seal-ring structure in a peripheral region of the 3D IC in the first and second IC dies. The seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate. The bonding forms a plurality of through silicon via (TSV) coupling structures at the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure by electrically and correspondingly connects a first plurality of TSV wiring layers and inter-wire vias and a second plurality of TSV wiring layers and inter-wire vias.
Public/Granted literature
- US20200035672A1 THROUGH SILICON VIA DESIGN FOR STACKING INTEGRATED CIRCUITS Public/Granted day:2020-01-30
Information query
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