Invention Grant
- Patent Title: Measurements of an integrated circuit chip and connected chip carrier to estimate height of interconnect
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Application No.: US15827082Application Date: 2017-11-30
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Publication No.: US10969222B2Publication Date: 2021-04-06
- Inventor: Elaine Cyr , Dominique L. Demers , Paul F. Fortier , Alexander Janta-Polczynski
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Roberts Calderon Safran & Cole, P.C.
- Agent Steven Meyers; Andrew M. Calderon
- Main IPC: G01B5/18
- IPC: G01B5/18 ; G01B21/16 ; H01L23/00 ; G01B11/06 ; G01B11/14

Abstract:
Systems and methods are provided for obtaining measurements of an integrated circuit chip and a connected carrier to obtain the measurements of the interconnect heights. More specifically, a method is provided that includes defining a top best fit reference plane and a bottom best fit reference plane, and adjusting the top best fit reference and the bottom best fit reference to be superposed to one another. The method further includes calculating first distances between each height measurement for a first set of points and the adjusted top best fit reference plane, and calculating second distances between each height measurement for a second set of points and the adjusted bottom best fit reference plane. The method further includes calculating height values of a gap or interconnect between the first substrate and the second substrate by subtracting the thickness of the first substrate and the second distances from the first distances.
Public/Granted literature
- US20180080765A1 MEASUREMENTS OF AN INTEGRATED CIRCUIT CHIP AND CONNECTED CHIP CARRIER TO ESTIMATE HEIGHT OF INTERCONNECT Public/Granted day:2018-03-22
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