- Patent Title: Reducing time of day latency variation in a multi processor system
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Application No.: US16275283Application Date: 2019-02-13
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Publication No.: US10969822B2Publication Date: 2021-04-06
- Inventor: Paul A. Ganfield , David J. Krolak , Luis A. Lastras-Montano
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Martin & Associates, LLC
- Agent Derek P. Martin
- Main IPC: G06F1/12
- IPC: G06F1/12 ; H04L1/00 ; G06F1/14

Abstract:
A time of day (TOD) synchronizer in a first processor transmits a latency measure message simultaneously on two links to a second processor. In response, the receiver in the second processor detects latency differential between the two links, detects the delay in the second processor, and sends the latency differential and delay to the first processor on one of the two links. The first processor stores TOD delay values in the two links that account for the latency differential between the two links. When a TOD message needs to be sent, a link loads a counter with its stored TOD delay value, then decrements the counter until the TOD message is ready to be sent. The resulting counter value is the receiver delay value, which is transmitted to the receiver as data in the TOD message, thereby reducing TOD jitter between the two links.
Public/Granted literature
- US20190179364A1 REDUCING TIME OF DAY LATENCY VARIATION IN A MULTI-PROCESSOR SYSTEM Public/Granted day:2019-06-13
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