- Patent Title: Extendable hardware queue structure and method of operation thereof
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Application No.: US15929206Application Date: 2020-01-23
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Publication No.: US10969996B1Publication Date: 2021-04-06
- Inventor: Moran Noiman , Michael Weiner , Eliya Babitsky
- Applicant: Marvell Israel (M.I.S.L) Ltd.
- Applicant Address: IL Yokne'am
- Assignee: Marvell Israel (M.I.S.L) Ltd.
- Current Assignee: Marvell Israel (M.I.S.L) Ltd.
- Current Assignee Address: IL Yokne'am
- Main IPC: G06F13/00
- IPC: G06F13/00 ; G06F3/06

Abstract:
A hardware queue for an integrated circuit device includes an internal queue memory and at least one external queue memory. The internal queue memory and the external queue memory are operated as a continuous hardware queue memory by monitoring occupancy of the internal queue memory and, based on that occupancy, controlling an internal tail pointer indicating a next write point for inserting new data into the internal queue memory, an internal head pointer indicating a next read point for extracting data from the internal queue memory based on order of insertion, at least one external tail pointer indicating a next write point for inserting new data into the external queue memory, at least one external head pointer indicating a next read point for extracting data from the external queue memory based on order of insertion, and wrap pointers indicating transitions between the internal queue memory and the external queue memory.
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