A memory controller controls an operation of a memory device including a plurality of planes, based on a request from a host. The memory controller includes a request storage unit and a request controller. The request storage unit stores a plurality of read requests received from the host. The request controller controls the request storage unit to perform a processing operation for a read request that has been map-cache-hit, more preferentially than a pairing operation for multi-plane reading, based on whether the plurality of read requests have been map-cache-hit.