A method of generating a layout diagram of an IC device includes assigning a leakage constraint to a first schematic net of the IC device and determining a violation of the leakage constraint based on a dummy gate region. The IC layout diagram includes the dummy gate region between a first component of the first schematic net and a second component of a second schematic net of the IC device. The method includes modifying the IC layout diagram in response to the leakage constraint violation, and generating a layout file based on the modified IC layout diagram.