Invention Grant
- Patent Title: Integrated circuit layout method, device, and system
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Application No.: US16553958Application Date: 2019-08-28
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Publication No.: US10970451B2Publication Date: 2021-04-06
- Inventor: Jian-Sing Li , Ting-Wei Chiang , Hui-Zhong Zhuang , Jung-Chan Yang , Li-Chun Tien , Ting Yu Chen , Tzu-Ying Lin
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Hauptman Ham, LLP
- Main IPC: G06F30/392
- IPC: G06F30/392 ; H01L27/02

Abstract:
A method includes positioning a first active region adjacent to a pair of second active regions in an initial integrated circuit (IC) layout diagram of an initial cell, to align side edges of the first active region and corresponding side edges of each second active region of the pair of second active regions along a cell height direction. The method further includes arranging at least one first fin feature in the first active region, to obtain a modified cell having a modified IC layout diagram. The side edges of the first active region and the corresponding side edges of each second active region extend along the cell height direction. A height dimension of the first active region in the cell height direction is less than half of a height dimension of each second active region of the pair of second active regions in the cell height direction. At least one of the positioning the first active region or the arranging the at least one first fin feature is executed by a processor.
Information query