Invention Grant
- Patent Title: Time borrowing between layers of a three dimensional chip stack
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Application No.: US16891027Application Date: 2020-06-02
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Publication No.: US10970627B2Publication Date: 2021-04-06
- Inventor: Steven L. Teig , Kenneth Duong , Javier DeLaCruz
- Applicant: Xcelsis Corporation
- Applicant Address: US CA San Jose
- Assignee: Xcelsis Corporation
- Current Assignee: Xcelsis Corporation
- Current Assignee Address: US CA San Jose
- Agency: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L25/065 ; H01L25/04 ; H01L25/07 ; H01L25/11 ; G06N3/063 ; G06N3/08 ; G06N3/04 ; G06F11/20 ; G06F11/14 ; H01L23/00 ; H01L25/075 ; H03K19/21

Abstract:
Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g., neural network) to perform particular operations (e.g., face recognition, voice recognition, etc.). For example, in some embodiments, the machine-trained parameters are weight values that are used to aggregate (e.g., to sum) several output values of several earlier stage processing nodes to produce an input value for a later stage processing node.
Public/Granted literature
- US20200293872A1 TIME BORROWING BETWEEN LAYERS OF A THREE DIMENSIONAL CHIP STACK Public/Granted day:2020-09-17
Information query
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