Invention Grant
- Patent Title: Semiconductor device
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Application No.: US16668768Application Date: 2019-10-30
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Publication No.: US10971219B2Publication Date: 2021-04-06
- Inventor: Makoto Yabuuchi , Shinji Tanaka
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JPJP2018-237192 20181219
- Main IPC: G11C11/419
- IPC: G11C11/419 ; G11C5/14 ; G11C11/412 ; H01L27/11

Abstract:
A semiconductor device capable of improving operating margins is provided. The semiconductor device comprises a memory circuit including a memory cell comprised of a SOTB transistor, and a mode designation circuit switching operation modes of the memory circuit for a first mode or a second mode. The memory circuit includes a substrate bias generation circuit supplying a substrate bias voltage to the SOTB transistor and a timing signal generation circuit generating a timing signal used for a reading operation or a writing operation of the memory circuit. The substrate bias generation circuit does not supply the substrate bias voltage to the SOTB transistor in the second mode.
Information query
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