A clock system including: an in-phase clock input and an in-phase clock output; a quadrature clock input and a quadrature clock output; a control loop configured to receive the in-phase clock output and the quadrature clock output, the control loop including a Boolean logic gate coupled to an operational amplifier (op-amp) through a low-pass filter; and an analog delay element coupled between the quadrature clock input and the quadrature clock output, the analog delay element comprising a plurality of capacitors.