An integrated circuit (IC) is provided. The IC includes a cache memory divided into a plurality of groups, and an address decoder. Each of the groups includes a plurality of sets, and one of the groups is assigned as a first group and the remaining groups are assigned as a plurality of second groups. The first group and the second groups are assigned in rotation for a plurality of time periods, and each of the groups is assigned in a corresponding single one of the time periods. The address decoder is configured to provide a physical address according to an access address of the cache memory. The sets of the first group that is assigned in a first time period are not overlapping with the sets of other first groups that are assigned in the time periods other than the first time period.