Invention Grant
- Patent Title: Deterministic test pattern generation for designs with timing exceptions
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Application No.: US16548172Application Date: 2019-08-22
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Publication No.: US10977400B2Publication Date: 2021-04-13
- Inventor: Wu-Tung Cheng , Kun-Han Tsai , Naixing Wang , Chen Wang , Xijiang Lin , Mark A. Kassab , Irith Pomeranz
- Applicant: Mentor Graphics Corporation
- Applicant Address: US OR Wilsonville
- Assignee: Mentor Graphics Corporation
- Current Assignee: Mentor Graphics Corporation
- Current Assignee Address: US OR Wilsonville
- Main IPC: G06F30/30
- IPC: G06F30/30 ; G06F119/12
Abstract:
Systems and methods for a deterministic automatic test generation (ATPG) process including Timing Exception ATPG (TEA). A method includes performing an automated test pattern generation (ATPG) process that uses timing exception information to generate a test pattern for a targeted fault of a circuit design with at least one timing exception path. The method includes testing the targeted fault of the circuit design using the test pattern to produce a test result for the targeted fault.
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